Olivetti PCS 286

Intel 80286 at 12 MHz with one wait state; AT-class platform with optional 80287 coprocessor.

1 MB standard, expandable to 4 MB on the motherboard and 16 MB in the system. BIOS tests base and extended memory during POST.

Integrated IDE/ATA. Documented configurations use two 1.44 MB floppy drives, or one floppy with a 20 MB Conner CP3022 or 40 MB CP346 hard disk.

G2 GC101A + GC102 set, later incorporated into the Headland family. BluMach uses 86Box's GC101/102/103 device plus Olivetti-specific IOC02 logic.

GC101 combines peripheral control, timing, arbitration and memory control; GC102 supplies address/data buffers and parity. The design supports up to 4 MB, matching the PCS 286 commercial limit.

The current model exposes 1ECh as EMS data, 1EDh as configuration index, 1EEh as EMS map index and 1EFh as configuration data. This is BluMach's functional interface and is not yet claimed as a complete physical decode of the motherboard.

GC101/GC102 Data Sheet, 55 pages, preserved inside BluMach

Sets 1.37 (one archival file was labelled 1.34) and 1.42. The 16 MHz PCS 286 S variant remains separate and is not presented as identical hardware.

Extended Setup (F1–F10) stores in CMOS the clock, hard disk (12h), floppy drives (10h), video (14h/1Ch), RAM test speed, RAM/IO frequency (12/12, 12/6 or 6/6 MHz: memory and I/O clocks, not the CPU clock), keyboard repeat rate, password and keyboard language. It has no shadow or EMS options. Drive B is offered only when the BIOS detects two floppy drives; with a hard disk only one internal drive fits, so the second would be external. In BluMach the frequency setting drives the I/O bus speed and, approximately, memory timing.

The observed Customer Test validates DMA controllers, keyboard, clock/calendar, protected mode and CMOS, and reports floppy, fixed-disk and configuration errors.

128 KB BIOS at E0000h–FFFFFh. Revision 1.42 comes from two 64 KB 27C512 EPROMs, LOW and HIGH, byte-interleaved. The older set identifies itself as 1.37 although its archival label said 1.34.

Test 6 writes the string RAM-REMAPPING at 60000h and checks whether it reappears at 80000h. The BIOS selects the DRAM configuration with bits 2, 4 and 7 of keyboard-controller port P2: it tries the 1 Mbit chip configuration first and, if the string is reflected, falls back to 256 Kbit. BluMach only reflects 60000h at 80000h with 1 MB fitted and while bit 7 is set. Until this version the alias was permanent: it took 128 KB of conventional memory and pushed 2 and 4 MB boards into the 256 Kbit configuration.

Ports 68h, 6Ah and 6Ch. Phoenix 1.42 expects the first 6Ah read to publish 04h (subsystem ready). The device also resets on warm reset so stale values cannot cause I/O CONTROLLER ERROR 2.

Routine at F000:D192. It sends FFh to the keyboard, receives FAh as ACK and then waits for AAh as BAT result. Keyboard Error 4 means exactly that FAh arrived but BAT did not finish before timeout; this finding allowed the sequence to be fixed without fabricating keystrokes.

Phoenix compares the BDA equipment word at 0040:0010 with CMOS 14h. For 80x25, one floppy and no coprocessor the base value is 0020h. CMOS 0Eh holds diagnostic state and 10h the floppy type; checksum covers 10h–2Dh and is stored at 2Eh/2Fh.

No valid 55 AAh option-ROM signature appears at C0000h. Historical halves named Video at E0000 and BIOS at F0000 are actually parts of system BIOS 1.37. Paradise/Olivetti initialization is integrated in the main ROM.

BIOS 1.42, POST, Extended Setup, MS-DOS boot and Customer Test execution with a 40 MB IDE disk.

The complete physical I/O decode, exact effect of some GC101A registers and authentic internal M5L8042-243P ROM remain to be documented. A functional approximation is used where no dump or schematic is available. The password keyboard-lock mode is not emulated, and the keyboard repeat rate follows the host computer.